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| CY7C604XX enCoReTM V Low Voltage Microcontroller Features Powerful Harvard Architecture Processor M8C processor speeds running up to 24 MHz Low power at high processing speeds Interrupt controller 1.71V to 3.6V operating voltage Temperature range: 0C to 70C Flexible On-Chip Memory Up to 32K Flash program storage * 50,000 Erase and write cycles * Flexible protection modes Up to 2048 bytes SRAM data storage In-System Serial Programming (ISSP) Complete Development Tools Free development tool (PSoC DesignerTM) Full featured, in-circuit emulator and programmer Full speed emulation Complex breakpoint structure 128K trace memory Precision, Programmable Clocking Crystal-less oscillator with support for an external crystal or resonator Internal 5.0% 6, 12, or 24 MHz main oscillator Internal low speed oscillator at 32 kHz for watchdog and sleep.The frequency range is 19 to 50 kHz with a 32 kHz typical value Programmable Pin Configurations 25 mA sink current on all GPIO Pull Up, High Z, Open Drain, CMOS drive modes on all GPIO Configurable inputs on all GPIO Low dropout voltage regulator for Port 1 pins. Programmable to output 3.0, 2.5, or 1.8V at the I/O pins Selectable, regulated digital I/O on Port 1 * Configurable input threshold for Port 1 * 3.0V, 20 mA total Port 1 source current * Hot-swappable 5 mA strong drive mode on Ports 0 and 1 Additional System Resources Configurable communication speeds 2 I C Slave * Selectable to 50 kHz, 100 kHz, or 400 kHz * Implementation requires no clock stretching * Implementation during sleep modes with less than 100 mA * Hardware address detection SPI master and SPI slave * Configurable between 93.75 kHz and 12 MHz Three 16-bit timers 8-bit ADC used to monitor battery voltage or other signals with external components Watchdog and sleep timers Integrated supervisory circuit enCoRe V LV Block Diagram enCoRe V Low Voltage CORE Port 4 Port 3 Port 2 Port 1 Port 0 Prog. LDO System Bus SRAM 2048 Bytes Interrupt Controller SROM Flash 32K Sleep and Watchdog CPU Core (M8C) 6/12/24 MHz Internal Main Oscillator 3 16-Bit Timers I2C Slave/SPI Master-Slave POR and LVD System Resets SYSTEM RESOURCES Cypress Semiconductor Corporation Document Number: 001-12395 Rev *H * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised January 30, 2009 [+] Feedback CY7C604XX Functional Overview The enCoRe V LV family of devices are designed to replace multiple traditional low voltage microcontroller system components with one, low cost single chip programmable component. Communication peripherals (I2C/SPI), a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts. The architecture for this device family, as illustrated in enCoRe V LV Block Diagram, is comprised of two main areas: the CPU core and the system resources. Depending on the enCoRe V LV package, up to 36 general purpose IO (GPIO) are also included. Enhancements over the Cypress's legacy low voltage microcontrollers include faster CPU at lower voltage operation, lower current consumption, twice the RAM and Flash, hot-swapable I/Os, I2C hardware address recognition, new very low current sleep mode, and new package options. Getting Started The quickest way to understanding the enCoRe V silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the enCoRe V integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information, along with detailed programming information, reference the PSoC Programmable System-on-Chip Technical Reference Manual, for CY8C28xxx PSoC devices. For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest enCoRe V device data sheets on the web at http://www.cypress.com. Development Kits Development Kits are available online from Cypress at www.cypress.com/shop and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. The enCoRe V LV Core The enCoRe V LV Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO (internal main oscillator) and ILO (internal low speed oscillator). The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a four-MIPS, 8-bit Harvard architecture microprocessor. System Resources provide additional capability, such as a configurable I2C slave and SPI master-slave communication interface and various system resets supported by the M8C. Training Free technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training. The training covers a wide variety of topics and skill levels to assist you in your designs. CyPros Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to www.cypress.com/cypros. Additional System Resources System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. The following statements describe the merits of each system resource: Solutions Library Visit our growing library of solution focused designs at www.cypress.com/solutions. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. 8-bit on-chip ADC shared between System Performance manager (used to calculate parameters based on temperature for flash write operations) and the user. The I2C slave and SPI master-slave module provides 50, 100, or 400 kHz communication over two wires. SPI communication over three or four wires runs at speeds of 46.9 kHz to 3 MHz (lower for a slower system clock). In I2C slave mode, the hardware address recognition feature reduces the already low power consumption by eliminating the need for CPU intervention until a packet addressed to the target device has been received. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. The 5V maximum input, 1.8, 2.5, or 3V selectable output, low dropout regulator (LDO) provides regulation for I/Os. A register controlled bypass mode enables the user to disable the LDO. Standard Cypress PSoC IDE tools are available for debugging the enCoRe V LV family of parts. Technical Support For assistance with technical issues, search KnowledgeBase articles and forums at www.cypress.com/support. If you cannot find an answer to your question, call technical support at 1-800-541-4736. Application Notes Application notes are an excellent introduction to the wide variety of possible PSoC designs. They are located here: www.cypress.com/psoc. Select Application Notes under the Documentation tab. Document Number: 001-12395 Rev *H Page 2 of 30 [+] Feedback CY7C604XX Development Tools PSoC Designer is a Microsoft(R) Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE runs on Windows XP or Windows Vista. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and built-in support for third-party assemblers and C compilers. PSoC Designer also supports C language compilers developed specifically for the devices in the enCoRe and PSoC families. Assemblers. The assemblers allow assembly code to be merged seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the enCoRe and PSoC families of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all the features of C tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program flash, read and write data memory, read and write I/O registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural help and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. In-Circuit Emulator A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and operates with all enCoRe and PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. PSoC Designer Software Subsystems Chip-Level View The chip-level view is a traditional integrated development environment (IDE) based on PSoC Designer 4.4. Choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. Configure the user modules for the chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration enables changing configurations at run time. System-Level View The system-level view is a drag-and-drop visual embedded system design environment based on PSoC Designer. Hybrid Designs You can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on-chip resources. All views of the project share common code editor, builder, and common debug, emulation, and programming tools. Code Generation Tools PSoC Designer supports multiple third-party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours. Document Number: 001-12395 Rev *H Page 3 of 30 [+] Feedback CY7C604XX Designing with PSoC Designer The development process for the enCoRe V device differs from that of a traditional fixed function microprocessor. Powerful PSoC Designer tools get the core of your design up and running in minutes instead of hours. The development process can be summarized in the following four steps: 1. Select Components 2. Configure Components 3. Organize and Connect 4. Generate, Verify, and Debug valuator functions. In the chip-level view, you perform the selection, configuration, and routing so that you have complete control over the use of all on-chip resources. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, you perform the "Generate Configuration Files" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. Both system-level and chip-level designs generate software based on your design. The chip-level design provides application programming interfaces (APIs) with high-level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. The system-level design also generates a C main() program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code. A complete code development environment allows you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside PSoC Designer's Debugger (access by clicking the Connect icon). PSoC Designer downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. Select Components The chip-level views provide a library of pre-built, pre-tested hardware peripheral components. These components are called "user modules." User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed-signal varieties. Configure Components Each of the components you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. The chip-level user modules are documented in data sheets that are viewed directly in PSoC Designer. These data sheets explain the internal operation of the component and provide performance specifications. Each data sheet describes the use of each user module parameter and contains other information you may need to successfully implement your design. Organize and Connect You build signal chains at the chip level by interconnecting user modules to each other and the I/O pins, or connect system-level inputs, outputs, and communication interfaces to each other with Document Number: 001-12395 Rev *H Page 4 of 30 [+] Feedback CY7C604XX Document Conventions Acronyms Used The following table lists the acronyms that are used in this document. Acronym API CPU GPIO ICE ILO IMO IO LSb LVD MSb POR PPOR PSoC(R) SLIMO SRAM Description application programming interface central processing unit general purpose IO in-circuit emulator internal low speed oscillator internal main oscillator input/output least significant bit low voltage detect most significant bit power on reset precision power on reset Programmable System-on-ChipTM slow IMO static random access memory Units of Measure A units of measure table is located in the Electrical Specifications section. Table 7 on page 14 lists all the abbreviations used to measure the enCoRe V LV devices. Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexadecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (for example, 01010100b' or `01000011b'). Numbers not indicated by an `h', `b', or 0x are decimal. Document Number: 001-12395 Rev *H Page 5 of 30 [+] Feedback CY7C604XX Pin Configuration 16-Pin Part Pinout Figure 1. CY7C60413 16-Pin enCoRe V LV Device Table 1. 16-Pin Part Pinout (QFN) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type I/O I/O IOHR IOHR IOHR IOHR Power IOHR IOHR IOHR Input IOHR Power IOHR IOHR IOHR Name P2[5] P2[3] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] XRES P0[4] Vdd P0[7] P0[3] P0[1] Description Digital I/O, Crystal Out (Xout) Digital I/O, Crystal In (Xin) Digital I/O, I2C SCL, SPI SS Digital I/O, I2C SDA, SPI MISO Digital I/O, SPI CLK Digital I/O, ISSP CLK, I2C SCL, SPI MOSI Ground Pin Digital I/O, ISSP DATA, I2C SDA, SPI CLK Digital I/O Digital I/O, optional external clock input (EXTCLK) Active high external reset with internal pull down Digital I/O Power Pin Digital I/O Digital I/O Digital I/O LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output. Document Number: 001-12395 Rev *H Page 6 of 30 [+] Feedback CY7C604XX 32-Pin Part Pinout Figure 2. CY7C60445 32-Pin enCoRe V LV Device P0[3] P0[5] P0[7] Vdd P0[6] 28 27 P0[4] 26 32 31 30 29 P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] P3[1] P1[7] 1 2 3 4 5 6 7 8 25 24 23 P0[2] Vss P0[0] P2[6] P2[4] P2[2] P2[0] P3[2] P3[0] XRES QFN (Top View) 22 21 20 19 18 17 9 10 11 12 13 14 P1[0] P1[2] 15 P1[4] P1[5] P1[1] P1[3] Vss Table 2. 32-Pin Part Pinout (QFN) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type IOH I/O I/O I/O I/O I/O I/O IOHR IOHR IOHR IOHR Power IOHR IOHR IOHR IOHR Name P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1](3, 4) Vss P1[0](3, 4) P1[2] P1[4] P1[6] Digital I/O Digital I/O Digital I/O, Crystal Out (Xout) Digital I/O, Crystal In (Xin) Digital I/O Digital I/O Digital I/O Digital I/O, I2C SCL, SPI SS Digital I/O, I2C SDA, SPI MISO Digital I/O, SPI CLK Digital I/O, ISSP CLK, I2C SCL, SPI MOSI Ground connection Digital I/O, ISSP DATA, I2C SDA, SPI CLK Digital I/O Digital I/O, optional external clock input (EXTCLK) Digital I/O Description Notes 1. During power up or reset event, device P1[0] and P1[1] may disturb the I2C bus. Use alternate pins if issues are encountered. 2. These are the in-system serial programming (ISSP) pins, that are not High Z at power on reset (POR) Document Number: 001-12395 Rev *H P1[6] 16 Page 7 of 30 [+] Feedback CY7C604XX Table 2. 32-Pin Part Pinout (QFN) (continued) Pin No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CP Type Reset Input I/O I/O I/O I/O I/O I/O IOH IOH IOH IOH Power IOH IOH IOH Power Power Name XRES P3[0] P3[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd P0[7] P0[5] P0[3] Vss Vss Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Supply voltage Digital I/O Digital I/O Digital I/O Ground connection Center pad must be connected to ground Description Active high external reset with internal pull down LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output. Notes 3. During power up or reset event, device P1[0] and P1[1] may disturb the I2C bus. Use alternate pins if issues are encountered. 4. These are the in-system serial programming (ISSP) pins, that are not High Z at power on reset (POR) Document Number: 001-12395 Rev *H Page 8 of 30 [+] Feedback CY7C604XX 48-Pin Part Pinout Figure 3. CY7C60455/CY7C60456 48-Pin enCoRe V LV Device P0[4] 39 P0[2] 38 P0[3] P0[5] P0[7] P0[1] 48 47 46 45 44 43 42 41 NC NC 40 P0[6] 37 NC P2[7] P2[5] P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P1[7] 1 2 3 4 5 6 7 8 9 P0[0] 36 35 34 33 32 Vdd Vss P2[6] P2[4] P2[2] P2[0] P4[2] P4[0] P3[6] P3[4] P3[2] P3[0] XRES P1[6] QFN (Top View) 31 30 29 28 27 26 25 10 11 12 13 14 15 16 17 18 19 20 21 22 P1[0] 23 24 P1[2] P1[3] P1[1] P1[5] Table 3. 48-Pin Part Pinout (QFN) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Type NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IOHR IOHR NC NC IOHR IOHR NC P2[7] P2[5] P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] NC NC P1[3] P1[1] (3, 4) Name No connection Digital I/O Description Digital I/O, Crystal Out (Xout) Digital I/O, Crystal In (Xin) Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O, I2C SCL, SPI SS Digital I/O, I2C SDA, SPI MISO No connection No connection Digital I/O, SPI CLK Digital I/O, ISSP CLK, I2C SCL, SPI MOSI Document Number: 001-12395 Rev *H P1[4] NC NC Vss NC Vdd NC Page 9 of 30 [+] Feedback CY7C604XX Table 3. 48-Pin Part Pinout (QFN) (continued) Pin No. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 CP Type Power NC NC Power IOHR IOHR IOHR IOHR XRES I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IOH IOH IOH IOH Power NC NC IOH IOH IOH Power IOH Power NC NC Vdd P1[0] P1[2] P1[4] P1[6] Ext Reset P3[0] P3[2] P3[4] P3[6] P4[0] P4[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd NC NC P0[7] P0[5] P0[3] Vss P0[1] Vss (3, 4) Name Vss Supply ground No connection No connection Supply voltage Description Digital I/O, ISSP DATA, I2C SDA, SPI CLK Digital I/O Digital I/O, optional external clock input (EXTCLK) Digital I/O Active high external reset with internal pull down Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Supply voltage No connection No connection Digital I/O Digital I/O Digital I/O Supply ground Digital I/O Center pad must be connected to ground LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output Document Number: 001-12395 Rev *H Page 10 of 30 [+] Feedback CY7C604XX Register Reference The section discusses the registers of the enCoRe V LV device. It lists all the registers in mapping tables, in address order. Register Conventions The register conventions specific to this section are listed in the following table. Table 4. Register Conventions Convention R W L C # Description Read register or bits Write register or bits Logical register or bits Clearable register or bits Access is bit specific Register Mapping Tables The enCoRe V LV device has a total register address space of 512 bytes. The register space is also referred to as IO space and is broken into two parts: Bank 0 (user space) and Bank 1 (configuration space). The XIO bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XIO bit is set, the user is said to be in the "extended" address space or the "configuration" registers. Document Number: 001-12395 Rev *H Page 11 of 30 [+] Feedback CY7C604XX Table 5. Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE Addr (0,Hex) 00 01 02 03 Access RW RW Name Addr (0,Hex) 40 41 42 43 Access Name Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF Access Name Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 Access PRT1DR PRT1IE 04 05 06 07 RW RW 44 45 46 47 PRT2DR PRT2IE 08 09 0A 0B RW RW 48 49 4A 4B I2C_XCFG I2C_XSTAT I2C_ADDR I2C_BP I2C_CP CPU_BP CPU_CP I2C_BUF CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK2 INT_MSK1 INT_MSK0 INT_SW_EN INT_VC RES_WDT INT_MSK3 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF RW R RW R R RW R RW RW RW RW RW RW RW # RW RW RW RW RW RW RW RW RW RC W RW PRT3DR PRT3IE 0C 0D 0E 0F RW RW 4C 4D 4E 4F PRT4DR PRT4IE 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 RW RW 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 SPI_TXR SPI_RXR SPI_CR 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F W R # 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F # Access is bit specific. PT0_CFG PT0_DATA1 PT0_DATA0 PT1_CFG PT1_DATA1 PT1_DATA0 PT2_CFG PT2_DATA1 PT2_DATA0 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF RW RW RW RW RW RW RW RW RW CPU_F F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD CPU_SCR1 CPU_SCR0 FE FF # # RL Gray fields are reserved and should not be accessed. Document Number: 001-12395 Rev *H Page 12 of 30 [+] Feedback CY7C604XX Table 6. Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 Addr (1,Hex) 00 01 02 03 Access RW RW Name Addr (1,Hex) 40 41 42 43 Access Name Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB Access Name Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB Access PRT1DM0 PRT1DM1 04 05 06 07 RW RW 44 45 46 47 PRT2DM0 PRT2DM1 08 09 0A 0B RW RW 48 49 4A 4B PRT3DM0 PRT3DM1 0C 0D 0E 0F RW RW 4C 4D 4E 4F PRT4DM0 PRT4DM1 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 RW RW 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 IO_CFG OUT_P1 DC DD DE DF RW RW OSC_CR0 ECO_CFG OSC_CR2 VLT_CR VLT_CMP E0 E1 E2 E3 E4 E5 E6 E7 RW # RW RW R IMO_TR ILO_TR SLP_CFG SLP_CFG2 SLP_CFG3 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 W W RW RW RW SPI_CFG 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F RW 69 6A 6B TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F # Access is bit specific. RW RW RW RW AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF CPU_F F7 F8 F9 FA FB FC FD FE FF RL Gray fields are reserved and should not be accessed. Document Number: 001-12395 Rev *H Page 13 of 30 [+] Feedback CY7C604XX Electrical Specifications This section presents the DC and AC electrical specifications of the enCoRe V LV devices. For the most up to date electrical specifications, verify that you have the most recent data sheet available by visiting the company web site at http://www.cypress.com. Figure 4. Voltage versus CPU Frequency 3.6V Figure 5. IMO Frequency Trim Options 3.6V lid ng Va rati n pe gio Re O Vdd Voltage Vdd Voltage SLIMO Mode = 01 SLIMO Mode = 00 SLIMO Mode = 10 1.71V 1.71V 750 kHz 3 MHz CPU Frequency 24 MHz 750 kHz 3 MHz 6 MHz 12 MHz 24 MHz IMO Frequency The following table lists the units of measure that are used in this chapter. Table 7. Units of Measure Symbol oC dB fF Hz KB Kbit kHz k MHz M A F H s V Vrms Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square Symbol W mA ms mV nA ns nV pA pF pp ppm ps sps s V Unit of Measure microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts Document Number: 001-12395 Rev *H Page 14 of 30 [+] Feedback CY7C604XX ADC Electrical Specifications Table 8. ADC Electrical Specifications Symbol Input Input Voltage Range Input Capacitance Resolution 8-Bit Sample Rate DC Accuracy DNL INL Offset Error Operating Current Data Clock 2.25 -1 -2 0 15 275 +2 +2 90 350 12 LSb LSb mV A MHz Source is chip's internal main oscillator. See AC Chip Level Specifications for accuracy. Not guaranteed. See DNL 24 30 12 0 1 5 1/(500fF*D 1/(400fF*D 1/(300fF*D ata-Clock) ata-Clock) ata-Clock) dB dB dB dB %FSR For any resolution Equivalent switched cap input resistance for 8-, 9-, or 10-bit resolution. For any configuration For any configuration 8 23.4375 Vss 1.3 5 V pF Bits ksps Data Clock set to 6 MHz. Sample Rate = 0.001/(2^Resolution/Data clock) This gives 72% of maximum code Description Min Typ Max Units Conditions Monotonicity Power Supply Rejection Ratio PSRR (Vdd>3.0V) PSRR (2.2 < Vdd < 3.0) PSRR (2.0 < Vdd < 2.2) PSRR (Vdd < 2.0) Gain Error Input Resistance Document Number: 001-12395 Rev *H Page 15 of 30 [+] Feedback CY7C604XX Electro Static Discharge Voltage (ESD) (6) .................. 2000V Latch-up Current (LU) (7) ........................................... 200 mA Maximum Ratings Storage Temperature (TSTG) (5)-55oC to 125oC (Typical +25oC) Supply Voltage Relative to Vss (Vdd) ............. -0.5V to +4.0V DC Input Voltage (VIO).................... Vss - 0.5V to Vdd + 0.5V DC Voltage Applied to Tri-state (VIOZ)Vss - 0.5V to Vdd + 0.5V Maximum Current into any Port Pin (IMIO). -25mA to +50 mA Operating Conditions Ambient Temperature (TA) .................................. 0oC to 70oC Operational Die Temperature (TJ)(8) ................... 0oC to 85oC DC Electrical Characteristics DC Chip Level Specifications Table 9 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 9. DC Chip Level Specifications Parameter Vdd IDD24 Description Supply Voltage Supply Current, IMO = 24 MHz Conditions See table titled DC POR and LVD Specifications on page 20. Conditions are Vdd = 3.0V, TA = 25oC, CPU = 24 MHz No I2C/SPI Conditions are Vdd = 3.0V, TA = 25oC, CPU = 12 MHz No I2C/SPI Conditions are Vdd = 3.0V, TA = 25oC, CPU = 6 MHz No I2C/SPI Vdd = 3.0V, TA = 25oC, IO regulator turned off Vdd = 3.0V, TA = 25oC, IO regulator turned off Min 1.71 - Typ - - Max 3.6 3.1 Units V mA IDD12 Supply Current, IMO = 12 MHz - - 2.0 mA IDD6 Supply Current, IMO = 6 MHz - - 1.5 mA ISB0 ISB1 Deep Sleep Current Standby Current with POR, LVD, and Sleep Timer - - 0.1 - - 1.5 A A Notes 5. Higher storage temperatures reduce data retention time. Recommended storage temperature is +25C 25C. Extended duration storage temperatures above 85C degrade reliability. 6. Human Body Model ESD. 7. According to JESD78 standard. 8. The temperature rise from ambient to junction is package specific. See on page 27. The user must limit the power consumption to comply with this requirement. Document Number: 001-12395 Rev *H Page 16 of 30 [+] Feedback CY7C604XX DC General Purpose I/O Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 1.71V to 3.6V and 0C TA 70C. Typical parameters apply to 3.3V at 25C. These are for design guidance only. Table 10. 3.0V to 3.6V DC GPIO Specifications Symbol RPU VOH1 VOH2 VOH3 Description Pull Up Resistor High Output Voltage Port 2 or 3 Pins High Output Voltage Port 2 or 3 Pins High Output Voltage Port 0 or 1 Pins with LDO Regulator Disabled for Port 1 High Output Voltage Port 0 or 1 Pins with LDO Regulator Disabled for Port 1 High Output Voltage Port 1 Pins with LDO Regulator Enabled for 3V Out High Output Voltage Port 1 Pins with LDO Regulator Enabled for 3V Out IOH < 10 A, maximum of 10 mA source current in all I/Os IOH = 1 mA, maximum of 20 mA source current in all I/Os IOH < 10 A, maximum of 10 mA source current in all I/Os IOH = 5 mA, maximum of 20 mA source current in all I/Os IOH < 10 A, Vdd > 3.1V, maximum of 4 I/Os all sourcing 5 mA IOH = 5 mA, Vdd > 3.1V, maximum of 20 mA source current in all I/Os Conditions Min 4 Vdd - 0.2 Vdd - 0.9 Vdd - 0.2 Typ 5.6 - - - Max 8 - - - Units k V V V VOH4 Vdd - 0.9 - - V VOH5 2.85 3.00 3.3 V VOH6 2.20 - - V VOH7 High Output Voltage IOH < 10 A, Vdd > 2.7V, maximum of 20 Port 1 Pins with LDO Enabled for 2.5V mA source current in all I/Os Out High Output Voltage IOH = 2 mA, Vdd > 2.7V, maximum of 20 Port 1 Pins with LDO Enabled for 2.5V mA source current in all I/Os Out IOH < 10 A, Vdd > 2.7V, maximum of 20 High Output Voltage Port 1 Pins with LDO Enabled for 1.8V mA source current in all I/Os Out High Output Voltage IOH = 1 mA, Vdd > 2.7V, maximum of 20 Port 1 Pins with LDO Enabled for 1.8V mA source current in all I/Os Out Low Output Voltage IOL = 25 mA, Vdd > 3.3V, maximum of 60 mA sink current on even port pins (for example, P0[2] and P1[4]) and 60 mA sink current on odd port pins (for example, P0[3] and P1[5]) 2.35 2.50 2.75 V VOH8 1.90 - - V VOH9 1.60 1.80 2.1 V VOH10 1.20 - - V VOL - - 0.75 V VIL VIH VH IIL CPIN Input Low Voltage Input High Voltage Input Hysteresis Voltage Input Leakage (Absolute Value) Pin Capacitance Package and pin dependent Temp = 25oC - 2.00 - - 0.5 - - 80 0.001 1.7 0.80 - 1 5 V V mV A pF Document Number: 001-12395 Rev *H Page 17 of 30 [+] Feedback CY7C604XX Table 11. 2.4V to 3.0V DC GPIO Specifications Symbol RPU VOH1 VOH2 VOH3 Description Pull Up Resistor High Output Voltage Port 2 or 3 Pins High Output Voltage Port 2 or 3 Pins High Output Voltage Port 0 or 1 Pins with LDO Regulator Disabled for Port 1 High Output Voltage Port 0 or 1 Pins with LDO Regulator Disabled for Port 1 High Output Voltage Port 1 Pins with LDO Enabled for 1.8V Out High Output Voltage Port 1 Pins with LDO Enabled for 1.8V Out Low Output Voltage Conditions Min 4 Vdd - 0.2 Typ 5.6 - - - Max 8 - - - Units k V V V IOH < 10 A, maximum of 10 mA source current in all I/Os IOH = 0.2 mA, maximum of 10 mA source Vdd - 0.4 current in all I/Os IOH < 10 A, maximum of 10 mA source Vdd - 0.2 current in all I/Os IOH = 2 mA, maximum of 10 mA source current in all I/Os IOH < 10 A, Vdd > 2.4V, maximum of 20 mA source current in all I/Os. IOH = 1 mA, Vdd > 2.4V, maximum of 20 mA source current in all I/Os IOL = 10 mA, maximum of 30 mA sink current on even port pins (for example, P0[2] and P1[4]) and 30 mA sink current on odd port pins (for example, P0[3] and P1[5]) Vdd - 0.5 VOH4 - - V VOH5A 1.50 1.80 2.10 V VOH6A 1.20 - - V VOL - - 0.75 V VIL VIH VH IIL CPIN Input Low Voltage Input High Voltage Input Hysteresis Voltage Input Leakage (Absolute Value) Capacitive Load on Pins Package and pin dependent Temp = 25oC - 1.6 - - 0.5 - - 80 0.001 1.7 0.72 - 1 5 V V mV A pF Document Number: 001-12395 Rev *H Page 18 of 30 [+] Feedback CY7C604XX Table 12. 1.71V to 2.4V DC GPIO Specifications Symbol RPU VOH1 VOH2 VOH3 Description Pull Up Resistor High Output Voltage Port 2 or 3 Pins High Output Voltage Port 2 or 3 Pins High Output Voltage Port 0 or 1 Pins with LDO Regulator Disabled for Port 1 High Output Voltage Port 0 or 1 Pins with LDO Regulator Disabled for Port 1 Low Output Voltage IOH = 10 A, maximum of 10 mA source current in all I/Os IOH = 0.5 mA, maximum of 10 mA source current in all I/Os IOH = 100 A, maximum of 10 mA source current in all I/Os IOH = 2 mA, maximum of 10 mA source current in all I/Os IOL = 5 mA, maximum of 20 mA sink current on even port pins (for example, P0[2] and P1[4]) and 30 mA sink current on odd port pins (for example, P0[3] and P1[5]) Conditions Min 4 Vdd - 0.2 Vdd - 0.5 Vdd - 0.2 Typ 5.6 - - - Max 8 - - - Units k V V V VOH4 Vdd - 0.5 - - V VOL - - 0.4 V VIL VIH VH IIL CPIN Input Low Voltage Input High Voltage Input Hysteresis Voltage Input Leakage (Absolute Value) Capacitive Load on Pins Package and pin dependent. Temp = 25oC - 0.65 x Vdd - - 0.5 - - 80 0.001 1.7 0.3 x Vdd - 1 5 V V mV A pF Document Number: 001-12395 Rev *H Page 19 of 30 [+] Feedback CY7C604XX DC POR and LVD Specifications Table 13 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 13. DC POR and LVD Specifications Symbol VPPOR0 VPPOR1 VPPOR2 VPPOR3 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 Description Vdd Value for PPOR Trip PORLEV[1:0] = 00b, HPOR = 0 PORLEV[1:0] = 00b, HPOR = 1 PORLEV[1:0] = 01b, HPOR = 1 PORLEV[1:0] = 10b, HPOR = 1 Vdd Value for LVD Trip VM[2:0] = 000b(10) VM[2:0] = 001b(11) VM[2:0] = 010b(12) VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b(13) (9) Min 1.61 Typ 1.66 2.36 2.60 2.82 2.45 2.71 2.92 3.02 3.13 1.9 1.8 Max 1.71 2.41 2.66 2.95 2.51 2.78 2.99 3.09 3.20 2.32 1.84 Units V V V V V V V V 2.40 2.64 2.85 2.95 3.06 1.84 1.75 DC Programming Specifications Table 14 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 14. DC Programming Specifications Symbol VddIWRITE IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashDR Description Supply Voltage for Flash Write Operations Supply Current During Programming or Verify Input Low Voltage During Programming or Verify Input High Voltage During Programming or Verify Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify(14) Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify(14) Output Low Voltage During Programming or Verify Output High Voltage During Programming or Verify Flash Write Endurance(16) Flash Data Retention(17) Min 1.71 - - VIH - - - VOH 50,000 10 (13) Typ - 5 - - - - - - - 20 Max - 25 VIL - 0.2 1.5 Vss + 0.75 Vdd - - Units V mA V V mA mA V V Cycles Years Notes 9. Vdd must be greater than or equal to 1.71V during startup, reset from the XRES pin, or reset from watchdog. 10. Always greater than 50 mV above VPPOR1 for falling supply. 11. Always greater than 50 mV above VPPOR2 for falling supply. 12. Always greater than 50 mV above VPPOR3 for falling supply. 13. Always greater than 50 mV above VPPOR0 voltage for falling supply. 14. Driving internal pull down resistor. 15. See appropriate DC General Purpose I/O Specifications table. For Vdd > 3V use VOH4 in Table 10 on page 16. Erase/write cycles per block. 17. Following maximum Flash write cycles at Tamb = 55C and Tj = 70C. 17 Document Number: 001-12395 Rev *H Page 20 of 30 [+] Feedback CY7C604XX AC Electrical Characteristics AC Chip Level Specifications Table 15 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 15. AC Chip Level Specifications Symbol FMAX FCPU F32K1 FIMO24 FIMO12 FIMO6 DCIMO TRAMP Description Maximum Operating Frequency(18) Maximum Processing Frequency(19) Internal Low Speed Oscillator Frequency Internal Main Oscillator Stability for 24 MHz 5%(20) Internal Main Oscillator Stability for 12 MHz(20) Internal Main Oscillator Stability for 6 MHz(20) Duty Cycle of IMO Supply Ramp Time Min 24 24 19 22.8 11.4 5.7 40 0 Typ - - 32 24 12 6.0 50 - Max - - 50 25.2 12.6 6.3 60 - Units MHz MHz kHz MHz MHz MHz % s AC General Purpose IO Specifications Table 16 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 16. AC GPIO Specifications Symbol FGPIO Description GPIO Operating Frequency Conditions Normal Strong Mode, Port 0, 1 Min 0 0 Normal Strong Mode, Port 2, 3 0 Typ - - Max 6 MHz for 1.71V TRise01 Rise Time, Strong Mode, Cload Vdd = 3.0 to 3.6V, 10% - 90% LDO enabled or disabled = 50 pF Ports 0 or 1 Vdd = 2.4 to 3.0V, 10% - 90% LDO enabled or disabled Rise Time, Strong Mode Low Supply, Cload = 50 pF Ports 0 or 1 Vdd = 1.71 to 3.0V, 10% - 90% LDO enabled or disabled 10 10 15 - - - 50 70 100 ns TRise01L ns TFall Fall Time, Strong Mode, Cload = Vdd = 3.0 to 3.6V, 10% - 90% 50 pF All Ports Vdd = 1.71 to 3.0V, 10% - 90% 10 10 - - 80 80 ns Notes 18. Digital clocking functions. 19. CPU speed. 20. Trimmed using factory trim values. Document Number: 001-12395 Rev *H Page 21 of 30 [+] Feedback CY7C604XX Figure 6. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRise23 TRise01 TFall AC External Clock Specifications Table 17 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 17. AC External Clock Specifications Symbol FOSCEXT - - - Frequency High Period Low Period Power Up IMO to Switch Description Min 0.750 20.6 20.6 150 Typ - - - - Max 25.2 5300 - - Units MHz ns ns s AC Programming Specifications Table 18 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 18. AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK1 TDSCLK2 Description Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK, 3.0V Page 22 of 30 [+] Feedback CY7C604XX Figure 7. Timing Diagram - AC Programming Cycle AC SPI Specifications Table 19 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 19. AC SPI Specifications Symbol FSPIM Description Maximum Input Clock Frequency Selection, 2.4V Notes 21. Output clock frequency is half of input clock rate. Document Number: 001-12395 Rev *H Page 23 of 30 [+] Feedback CY7C604XX AC I2C Specifications Table 20 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 20. AC Characteristics of the I2C SDA and SCL Pins Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Description SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Setup Time for a Repeated START Condition Data Hold Time Data Setup Time Setup Time for STOP Condition Bus Free Time Between a STOP and START Condition Pulse Width of Spikes are Suppressed by the Input Filter Standard Mode Min Max 0 100 4.0 - 4.7 4.0 4.7 0 250 4.0 4.7 - - - - - - - - - Fast Mode Min Max 0 400 0.6 - 1.3 0.6 0.6 0 100(22) 0.6 1.3 0 - - - - - - - 50 Units kHz s s s s s ns s s ns Figure 8. Definition of Timing for Fast/Standard Mode on the I2C Bus SDA TLOWI2C TSUDATI2C THDSTAI2C TSPI2C TBUFI2C SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C Sr P S Notes 22. A fast mode I2C bus device can be used in a standard mode I2C bus system, but the requirement tSU;DAT S 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification) before the SCL line is released. Document Number: 001-12395 Rev *H Page 24 of 30 [+] Feedback CY7C604XX Package Diagram This section illustrates the packaging specifications for the enCoRe V LV device, along with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the enCoRe V LV emulation tools and their dimensions, refer to the development kit. Packaging Dimensions Figure 9. 16-Pin (3 x 3 mm) QFN (001-09116) 001-09116 *D Document Number: 001-12395 Rev *H Page 25 of 30 [+] Feedback CY7C604XX Figure 10. 32-Pin (5 x 5 x 0.55 mm) QFN (001-42168) 001-42168 *C Document Number: 001-12395 Rev *H Page 26 of 30 [+] Feedback CY7C604XX Figure 11. 48-Pin (7 x 7 x 0.9 mm) QFN (001-13191) 001-13191 *C Package Handling Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving the factory. A label on the package has details about the actual bake temperature and the minimum bake time to remove this moisture. The maximum bake time is the aggregate time that the parts exposed to the bake temperature. Exceeding this exposure may degrade device reliability. Table 21.Package Handling Parameter TBAKETEMP TBAKETIME Description Bake Temperature Bake Time See package label Minimum Typical 125 Maximum See package label 72 Unit oC hours Document Number: 001-12395 Rev *H Page 27 of 30 [+] Feedback CY7C604XX Thermal Impedances Package 16 QFN 32 QFN(24) 48 QFN(24) Typical JA (23) 32.69 oC/W 19.51 oC/W 17.68 oC/W Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Package 16 QFN 32 QFN 48 QFN Minimum Peak Temperature(25) 240 C 240oC 240oC o Maximum Peak Temperature 260oC 260oC 260oC Ordering Information Ordering Code CY7C60413-16LKXC Package Information 16-Pin QFN (3x3 mm) Flash 8K 8K 16K 16K 16K 16K 32K 32K SRAM 1K 1K 1K 1K 1K 1K 2K 2K No. of GPIOs 13 13 28 28 36 36 36 36 Target Applications Feature-rich Wireless Mouse Feature-rich Wireless Mouse Feature-Rich Wireless Mouse Feature-Rich Wireless Mouse Mid-Tier Wireless Keyboard Mid-Tier Wireless Keyboard Feature-Rich Wireless Keyboard Feature-Rich Wireless Keyboard CY7C64013-16LKXCT 16-Pin QFN (3X3 mm) CY7C60445-32LQXC 32-Pin QFN (5x5x0.55 mm) CY7C60445-32LQXCT 32-Pin QFN - (Tape and Reel) (5x5x0.55 mm) CY7C60455-48LTXC CY7C60455-48LTXCT CY7C60456-48LTXC CY7C60456-48LTXCT 48-Pin QFN (7x7x0.9 mm) 48-Pin QFN - (Tape and Reel) (7x7x0.9 mm) 48-Pin QFN (7x7x0.9 mm) 48-Pin QFN - (Tape and Reel) (7x7x0.9 mm) Notes 23. TJ = TA + Power x JA. 24. To achieve the thermal impedance specified for the package, solder the center thermal pad to the PCB ground plane. 25. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 5C with Sn-Pb or 245 5C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. Document Number: 001-12395 Rev *H Page 28 of 30 [+] Feedback CY7C604XX Document History Page Document Title: CY7C604XX, enCoReTM V Low Voltage Microcontroller Document Number: 001-12395 Rev. ** *A *B ECN No. 626516 735721 1120504 Orig. of Change TYJ TYJ/ARI ARI Submission Date See ECN See ECN See ECN New data sheet Added new block diagram, replaced TBDs, corrected values, updated pinout information, changed part number to reflect new specifications. Corrected the description to pin 29 on Table 1, the Typ/Max values for ISB0 on the DC chip-level specifications, and the Min voltage value for VddIWRITE in the DC Programming Specifications table. Corrected Flash Write Endurance minimum value in the DC Programming Specifications table. Corrected the Flash Erase Time max value and the Flash Block Write Time max value in the AC Programming Specifications table. Implemented new latest template. Corrected the description to pin 13, 29 on Table 1 and 22,44 on Table 2. Added sections Register Reference, Register Conventions and Register Mapping Tables. Corrected Max values on the DC Chip-Level Specifications table. Changed TERASEB parameter, max value to 18ms in Table 13, AC Programming Specification. Post to www.cypress.com Updated Ordering Code table: - Ordering code changed for 32-QFN package: From -32LKXC to -32LTXC - Added a new package type - "LTXC" for 48-QFN - Included Tape and Reel ordering code for 32-QFN and 48-QFN packages Changed active current values at 24, 12 and 6MHz in table "DC Chip-Level Specifications" - IDD24: 2.15 to 3.1mA - IDD12: 1.45 to 2.0mA - IDD6: 1.1 to 1.5mA Added information on using P1[0] and P1[1] as the I2C interface during POR or reset events Converted from Preliminary to Final ADC resolution changed from 10-bit to 8-bit On Page1, SPI Master and Slave - speeds changed Rephrased battery monitoring clause in page 1 to include "with external components" Included ADC specifications table Voh5, Voh7, Voh9 specs changed Flash data retention - condition added to Note [15] Input leakage spec changed to 25 nA max Under AC Char, Frequency accuracy of ILO corrected GPIO rise time for ports 0,1 and ports 2,3 made common AC Programming specifications updated Included AC Programming cycle timing diagram AC SPI specification updated Spec change for 32-QFN package Input Leakage Current maximum value changed to 1 uA Maximum specification for VOH5A parameter changed from 2.0 to 2.1V Minimum voltages for FSPIM and FSPIS specifications changed from 1.8V to 1.71V (Table 18) Updated VOHV parameter in Table 13 Updated Thermal impedance values for the packages - Table 20. Update Development Tools, add Designing with PSoC Designer. Edit, fix links and table format. Update TMs. Update maximum data in Table 12. DC POR and LVD Specifications. Description of Change *C 1225864 AESA/ARI See ECN *D *E *F 1446763 1639963 2138889 AESA AESA TYJ/PYRS See ECN See ECN See ECN *G 2583853 TYJ/PYRS/ HMT 10/10/08 Document Number: 001-12395 Rev *H Page 29 of 30 [+] Feedback CY7C604XX Document Title: CY7C604XX, enCoReTM V Low Voltage Microcontroller Document Number: 001-12395 *H 2653717 DVJA/PYRS 02/04/09 Changed master page from CY7C60445, CY7C6045X to CY7C604XX. Updated Features, Functional Overview, Development Tools, and Designing with PSoC Designer sections. Removed `GUI - graphical user interface' from Document Conventions acronym table. Added Figure 1 and Table 1 (16-pin part information) to Pin Configurations section. Removed `O - Only a read/write register or bits' in Table 4 Edited Table 8: removed 10-bit resolution information and corrected units column. Added Figure 9 (16-pin part information) to Package Dimensions section. Added `Package Handling' section. Added 8K part `CY7C60413-16LKXC' to Ordering Information. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb (c) Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-12395 Rev *H Revised January 30, 2009 Page 30 of 30 enCoReTM, PSoC DesignerTM and Programmable System-on-ChipTM are trademarks and PSoC(R) is a registered trademark of Cypress Semiconductor Corporation. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback |
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